Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - verilog ip

Search list

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] RealizationofdigitaldownconversionbyFPGA

Description: 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital down conversion method, and completed its main modules of simulation and debugging, and initial system-level verification.
Platform: | Size: 162816 | Author: 于银 | Hits:

[VHDL-FPGA-Verilog] i2c_ip

Description: I2C的ip核，Verilog实现，可以直接用在你的项目中。I2C是一种简单实用的通讯协议。-I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol.
Platform: | Size: 2207744 | Author: caibaiyin | Hits:

[VHDL-FPGA-Verilog] NAND_IP

Description: Nand flash VHDL code and Nand flash verilog code
Platform: | Size: 22528 | Author: psungil | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] Verilog_UDP

Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Platform: | Size: 125952 | Author: 龙也 | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[Other] altera_nand_controller

Description: Altera合作伙伴Eureka Technology.和Cast Inc.为Altera FPGA芯片定制的Nand flash controller IP core-Altera partner Eureka Technology. And the Cast Inc. For the Altera FPGA chip custom Nand flash controller IP core
Platform: | Size: 296960 | Author: Trevor | Hits:

[VHDL-FPGA-Verilog] Ipcoredesign

Description: 微电子/软硬IP核设计：IP核脚本指南，模型开发指南-Microelectronics/soft and hard IP core design: IP core Scripting Guide, Model Development Guide
Platform: | Size: 581632 | Author: qq | Hits:

[VHDL-FPGA-Verilog] fsk

Description: 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
Platform: | Size: 1024 | Author: Sapphire | Hits:

[VHDL-FPGA-Verilog] xapp655

Description: xapp655 from xilinx website: Mixed-Version IP Router (MIR) in Verilog
Platform: | Size: 54272 | Author: bugidan | Hits:

[VHDL-FPGA-Verilog] CANProtocolControllerIPCoreinVerilog

Description: 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
Platform: | Size: 67584 | Author: Nicholas | Hits:

[VHDL-FPGA-Verilog] xge_mac

Description: 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below. . |-- doc - Documentation files | |-- rtl | |-- include - Verilog defines and utils | `-- verilog - Verilog source files for xge_mac | |-- sim | |-- systemc - SystemC simulation directory | `-- verilog - Verilog simulation directory | `-- tbench |-- systemc - SystemC test-bench source files `-- verilog - Verilog test-bench source files ------------------------ 2. Simulation ------------------------ There are two simulation environments that can be used to validate the code. The verilog simulation is very basic and meant for those who want to look at how the MAC operates without going through the effort of setting up SystemC. The SystemC environment is more sophisticated and covers
Platform: | Size: 899072 | Author: xuchao | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
Platform: | Size: 896000 | Author: panzhijian | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system.
Platform: | Size: 10980352 | Author: 海到无涯 | Hits:

[VHDL-FPGA-Verilog] TERASIC_AUDIO

Description: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Platform: | Size: 125952 | Author: changjiang | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Platform: | Size: 3072 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:
« 1 2 3 4 5 67 8 9 10 11 ... 18 »

CodeBus www.codebus.net